Boundary scan testing is well known. Boundary scan testing uses boundary scan shift registers that are built into each integrated circuit. FIG. 1 shows a conventional IC device 13 including boundary-scan register 11 interposed between the device I/O pins 12 and core 10, which may be programmable memory latches in the case of programmable devices. Data can be directly transferred between memory latches and the boundary scan register through interconnect 15.
FIG. 2 depicts a conventional IEEE 1149.1 compliant device architecture 31 that is referred to as a “boundary-scan architecture”. Boundary-scan architecture 31 includes a Test Access Port (TAP) 30, a TAP controller 20, an instruction register 26, instruction decode logic 25, a data register bank 24, and an output stage comprising a multiplexer 27, a flip-flop 28, and a tristate buffer 29. Although instruction decode logic 25 is shown as being separate from instruction register 26, instruction decode logic 25 may also be considered to be part of instruction register 26. Data register bank 24 includes the boundary-scan register 22 described above, and a bypass register 21. Bypass register 21 is a single bit shift register not associated with the IC core logic (memory latches) or I/O pins. Its purpose is to provide an alternate serial path between TDI and TDO pins of a JTAG-compliant device. As described below, only one of the registers in data bank 24 forms the serial path between TDI and TDO at any given time.
The TAP 30 is the interface between the boundary-scan architecture 31 and the five IC device pins required by IEEE 1149.1: test data in (TDI) and test data out (TDO) pins described above, test clock (TCK) pin, test mode select (TMS) pin, and one optional pin test reset (TRST) pin.
FIG. 3 depicts all possible states of the TAP controller 20, which is a sixteen-state state machine driven by the TCK and TMS signals asserted at the respective TCK and TMS pins of the IC device. The TAP controller 20 transitions from an existing state to one of the two possible states at the rising edge of the TCK signal based on the level of the TMS signal. Of the sixteen TAP controller states, one state is used to reset the test logic “Test-Logic Reset”, and another state is an idle state “Run-Test/Idle” from which either an instruction register scan or a data register scan can be selected. Of the remaining fourteen states, seven are used to perform a data register scan (from “Select DR Scan” to “Update DR”) and seven are used to perform an instruction register scan (from “Select IR Scan” to “Update IR”).
Instruction register scan and data register scan are symmetrical operations consisting of cycling the TAP controller 20 through a sequence of states to perform sample, shift, and transfer operations within the indicated register. In the case of an instruction register scan, the TAP controller 20 enters into a “Capture IR” state in which it issues an instruction register control signal to cause the instruction register to sample device status information. Then, in a “Shift IR” state, the device status information is shifted out of the instruction register via the TDO pin while a sequence of bits representing a new instruction is concurrently shifted into the instruction register via the TDI pin. After the new instruction has been shifted into the instruction register, it is transferred to a bank of output elements included in the instruction register 26 during an “Update IR” state of the TAP controller 20.
The instruction transferred to the bank of output elements in instruction register 26 is decoded by instruction decode logic 25 to select one of the registers in data register bank 24 to form a serial path between the TDI and TDO pins of the IC device through multiplexer 23, which is controlled by signals coming from instruction decode logic 25, to pass the output of either the boundary scan register 22 or the bypass register 21 to the output stage. As discussed below, the instruction in instruction register 26 is also decoded by instruction decode logic 25 to select the source of data shifted into the boundary scan register.
When the TAP controller 20 is sequenced through a data register scan, the TAP controller 20 issues control signals to each of the data registers included in data register bank 24. As discussed above, only one of the data registers from data register bank 24 is selected to form the serial data path between TDI and TDO at any given time, and the non-selected register is not disturbed during the data register scan. When the bypass register 21 is selected, the serial data path of the device is reduced to a single storage element, and data shifted through the bypass register 21 does not interfere with the normal operation of the device.
When the boundary scan register 11 in FIG. 1 is the data register selected to form the serial path between the TDI and TDO pins of the IC, sample, shift, and update operations similar to those performed in the instruction register 26 in FIG. 2 are performed. First, in a “Capture DR” state, the boundary scan register 11 samples the parallel data from the I/O 12 of the programmable device, if that portion of the boundary scan register is programmed as input, or samples the parallel data through interconnect 15, between boundary scan register 11 and memory latches 10, if that portion of the boundary scan cell is programmed as output. Then, in a “Shift DR” state, the boundary scan register 11 shifts a sequence of bits via TDI while concurrently shifting the values sampled during the “Capture DR” state out of the boundary scan register 11 via TDO. Finally, during the “update DR” state, the boundary scan register transfers the data to a bank of elements within the boundary scan register 11.
To comply with IEEE 1149.1, in FIG. 2 the boundary scan architecture 31 must be capable of carrying out three instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST. The BYPASS instruction is used to select the bypass register 21 to form a serial path between TDI and TDO. The SAMPLE/PRELOAD instruction is used to select the boundary scan register 22 to form a serial path between TDI and TDO, and to permit the parallel data to be sampled in the boundary scan register 22 without interfering with the normal operation of the IC. The SAMPLE/PRELOAD instruction further permits the boundary scan register 22 to be loaded with a sequence of bits to be later output at the parallel output of boundary scan register 22. This operation is called “preload”.
During the EXTEST instruction, the external data coming to the device at the input pins, which is the response of the applied test vector from other ICs on the same board to test the interconnects between ICs, is captured in boundary scan register 22 in the “Capture DR” state of TAP controller 20 and shifted out from boundary scan register 22 in the “Shift DR” state of the TAP controller 20 through the TDO pin and at the same time a new test vector is shifted into the boundary scan register 22 through the TDI pin to apply it on output pins in the “Update DR” state of the TAP controller 20.
The main problem with the existing IEEE 1149.1 architecture is the use of an excessive number of clock (TCK) cycles, which is equal to the number of boundary scan cells present in boundary scan register 22. To apply one test vector and receive one response, one has to travel the full length of boundary scan register. There is always a need to reduce clock cycles and thus to reduce testing time.
U.S. Pat. No. 6,266,801 provides a design to communicate with a plurality of tristate output buffers that are configured to receive a control signal and a data signal from an associated one of the plurality of data output boundary scan cells in order to reduce adverse timing impacts of conventional boundary scan cells. However, it employs large circuitry.
U.S. Pat. No. 5,355,369 speeds the testing of high-speed core logic circuitry by transferring the test program to a special test data register, which downloads the program to the logic circuitry under test, and uploads the results. However, it uses large numbers of user's I/Os and also does not reduce the scan path.